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[VHDL-FPGA-Verilog] uart8

Description: 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。-Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
Platform: | Size: 876544 | Author: 张键 | Hits:

[VHDL-FPGA-Verilog] FIFO_EMIF

Description: 实现FPGA通过EMIF总线给DSP定期发送数据的功能-FPGA implementation through the EMIF bus regularly send data to the DSP function
Platform: | Size: 1480704 | Author: 徐成发 | Hits:

[VHDL-FPGA-Verilog] fifotop

Description: 基于FPGA编写的VHDL语言，FIFO代码程序。 程序完整。-VHDL-based FPGA written language, FIFO procedure code. Complete the procedure.
Platform: | Size: 2100224 | Author: 李芳 | Hits:

[VHDL-FPGA-Verilog] SOPC_Builder

Description: SOPC架构建立实例，针对altera公司的DE2开发板，其他开发系统也可以用-based FPGA , SOPC construct experiment
Platform: | Size: 2323456 | Author: zhaoqian | Hits:

[VHDL-FPGA-Verilog] FPGA_Design_Guide_Chapter1_Westor

Description:
Platform: | Size: 2136064 | Author: 陈枫 | Hits:

[VHDL-FPGA-Verilog] ASYNCFIFO

Description: 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
Platform: | Size: 75776 | Author: Denny | Hits:

[VHDL-FPGA-Verilog] NIOS_JTAG_UART

Description: FPGA开发板上的JTAG——UART完成的工程设计，包括CPU内核设计合软件设计-FPGA development board JTAG- UART completed the engineering design, including the CPU core design combined software design
Platform: | Size: 7814144 | Author: 张一 | Hits:

[VHDL-FPGA-Verilog] 8fifo

Description: 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code
Platform: | Size: 3072 | Author: qaz | Hits:

[VHDL-FPGA-Verilog] fifi

Description: FIFO code written in VHDL
Platform: | Size: 11264 | Author: Harini | Hits:

[VHDL-FPGA-Verilog] fpgafifo

Description: 基于fpga 实现 fifo 基于FPGA的非对称同步FIFO设计-Fpga-based FPGA-based realization of fifo asymmetrical design of synchronous FIFO
Platform: | Size: 9216 | Author: 沈 | Hits:

[VHDL-FPGA-Verilog] fifo_sync

Description: 用VHDL语言编写的FPGA程序,实现异步FIFO的功能。这个程序设计十分巧妙，精简。 -vhdl fifo sound code
Platform: | Size: 1024 | Author: zxb | Hits:

[VHDL-FPGA-Verilog] THS1206

Description: FPGA来实现数据采集，AD采用TI公司的THS1206，高速并行AD，内含16字FIFO，降低硬件复杂度。-FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.
Platform: | Size: 1024 | Author: LX | Hits:

[Program doc] 68013_SlaveFIFO

Description: cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写-cy7c68013 slave fifo mode code ,written by hard ware language
Platform: | Size: 2151424 | Author: 杨瑞 | Hits:

[VHDL-FPGA-Verilog] fifo_test

Description: FIFO读写verilog程序，经本人验证，能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.
Platform: | Size: 2048 | Author: saul | Hits:

[VHDL-FPGA-Verilog] yuyincaiji

Description: 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data storage, faster, 256K* 16Bit selected the SRAM 2. In order to reduce the complexity of single-chip control, the use of the FPGA to control the SRAM The read and write operations, saving a lot of microcontroller I/O resources 3. to future high-speed data storage, the design into the fifo, its width and depth can be set up in the process of free, convenient and flexible.
Platform: | Size: 804864 | Author: song | Hits:

[VHDL-FPGA-Verilog] Asynchronous_FIFO_v6_1

Description: 详细介绍了异步FIFO的设计方法,以及fpga的仿真波形-Described in detail the design of asynchronous FIFO method and the simulation waveform fpga
Platform: | Size: 133120 | Author: wushaojie | Hits:

[VHDL-FPGA-Verilog] mem_ctrl_latest.tar

Description: 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
Platform: | Size: 331776 | Author: zhangsan | Hits:

[VHDL-FPGA-Verilog] trunk-hdlc

Description: 高级链路层协议的实现，vhdl，fpga-- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern is assumed only after the end of a frame which is signaled by an abort signal - Zero insertion - Abort pattern generation and checking - Address insertion and detection by software - CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used) - FIFO buffers and synchronization (External) - Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted) - Q.921, LAPB and LAPD compliant. - For complete specifications refer to spec document
Platform: | Size: 188416 | Author: | Hits:

[Books] usb

Description: 在高速的数据采集或传输中，目前使用较多的都是采用USB 2．0接口控制器和FPGA或DSP实现的，本设计在USB 2．0接口芯片CY7C68013的Slave FIFO模式下，利用FPGA作为外部主控制器实现对FX2 USB内部的FIFO进行控制，以实现数据的高速传输。该模块可普遍适用于基于USB 2．0接口的高速数据传输或采集中。-In the high-speed data acquisition or transmission, the currently used are based on more USB 2.0 interface controller and the FPGA or DSP implementation, the design USB 2.0 interface chip CY7C68013 of the Slave FIFO mode, the use of FPGA as a the external FX2 USB host controller to realize the internal FIFO control, in order to achieve high-speed data transmission. The module can be generally applied based on high-speed USB 2.0 interface, transfer or acquisition of data.
Platform: | Size: 894976 | Author: jiang_jennifer | Hits:

[source in ebook] T2_USB_IN

Description: CY7C68013A提供的端口FIFO的读写操作，与普通FIFO读写操作方式一样。CY7C68013A为每个端口提供了“空”标志、“满”标志和“ 可编程级”标志。FPGA检测这些信号，用于控制读写的过程-CY7C68013A available port FIFO read and write operations, and general FIFO read and write operations the same way. CY7C68013A for each port provide a " empty" signs, " full" signs and " programmable-class" logo. FPGA detect these signals, used to control the process of reading and writing
Platform: | Size: 1382400 | Author: jiang | Hits:
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